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Senior ASIC Design Engineer

MACOM

Newport Beach, CA, US
  • Job Type: Full-Time
  • Function: Engineering Hardware
  • Industry: Semiconductors & Electronics
  • Post Date: 08/03/2022
  • Website: macomtech.com
  • Company Address: 100 Chelmsford Street, Lowell, MA, 01851

About MACOM

MACOM designs and manufactures semiconductor products for Data Center, Telecommunication and Industrial and Defense applications.

Job Description

MACOM designs and manufactures semiconductor products for Data Center, Telecommunication and Industrial and Defense applications. Headquartered in Lowell, Massachusetts, MACOM has design centers and sales offices throughout North America, Europe and Asia. MACOM is certified to the ISO9001 international quality standard and ISO14001 environmental management standard.

MACOM has more than 65 years of application expertise with multiple design centers, Si, GaAs and InP fabrication, manufacturing, assembly and test, and operational facilities throughout North America, Europe, and Asia. Click here to view our facilities. In addition, MACOM offers foundry services that represents a key core competency within our business.

MACOM sells and distributes products globally via a sales channel comprised of a direct field sales force, authorized sales representatives and leading industry distributors. Our sales team is trained across all of our products to give our customers insights into our entire portfolio.

MACOM is an Equal Opportunity Employer.

We consider applicants for all positions without regard to race, color, religion, creed, gender, national origin, age, disability, marital status or veteran status or any other legally protected status.

Senior ASIC  Design Engineer

Job Description:

The selected candidate will be an individual contributor who is responsible for RTL coding and functional verification as well as working with the digital team to complete the ASIC design flow to deliver digital IP blocks to HPA developing products.

  •  Responsible for Implementing and delivering verified RTL blocks given architecture and Design specification requirements.
  • Responsible for RTL design/coding.
  • Responsible for writing functional verification plans.
  • Responsible for writing digital design spec.
  • Responsible for planning & working with other team members to complete the ASIC Design Flow: Synthesizing, DFT (MBIST, SCAN & JTAG), Formal Verification (LEC) and post layout static timing check as well as gate level simulation.

Job Requirements:

  •  Minimum of 2 years experiences with ASIC Flow design focusing on RTL coding and verification.
  • BSEE is required. MSEE is preferred
  • Fluency with Verilog, System Verilog and familiar with synthesis, formal verification, static timing analysis and timing constraints.
  • Experience with scripting (Perl, TCL, Python) is preferred.
  • Familiarity with design tools for simulation, debugging, synthesis and timing analysis.
  • Knowledge of C/C++/systemC and DSP algorithm modeling is a plus.
  • Ability to work under pressure and adapt within a team environment.
  • Good written and verbal communication skills, being able to deliver high quality output against aggressive schedule.

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