ASIC Design Verification Engineer at Acacia Communications
Maynard, MA, US

Founded by prominent industry experts Acacia designs, develops, manufactures, and sells advanced solutions to the optical transport and network infrastructure. Our products incorporate sophisticated signal processing and photonic integration for the 100G, 400G and 1T bit speed fiber optic transmission market deployed in data center, metro, long-haul and ultra-long haul telecommunication networks.

 

In 2014 Inc. 500 List of Fastest Growing Private Companies in America, Acacia Communications Ranked #5.  Acacia ranked #1 among Massachusetts headquartered based companies and #1 in the telecommunications industry.  Acacia Communications listed on the public markets on May 13, 2016 (Nasdaq: ACIA).

 

Our mission is to develop and market intelligent subsystems for ultra-high speed optical interconnect.  We are looking for experienced enthusiastic people with high energy and a team attitude who have the right experience and want to work at the forefront of fiber optic transmission subsystems. 

 

Job Description:

 

The ASIC Design Verification Engineer will be a member of a small, multi-disciplinary team working on next generation 100G-1T coherent optical communications products.  His/her primary role will be to write and execute verification test plans for large, highly complex ASICs that are used in these next generation telecom systems.

 

This engineer must be able to operate independently with minimal supervision in a fast-paced, dynamic and highly technical start-up environment. A successful candidate will be highly self-motivated, collaborative and passionate about delivering the most advanced high speed optical products in the world. Knowledge of object-oriented verification methodologies is required.

Key Essential Functions:

  • Develop detailed and comprehensive test plans
  • Develop verification test benches
  • Timely execution of test plans
  • Participate in, and assist in, FPGA emulation efforts
  • Assist chip level design tradeoffs by working with design engineers
  • Participate in review of design verification coding and coverage metrics

 

Minimum Qualifications, Experience, Skills, Education and Certifications:

 

  • Bachelors or Masters degree majoring in Computer Science, Computer Engineering, or Electronic or Electrical Engineering with 5 or more years of experience.
  • Experience with the latest ASIC verification methodologies, tools and scripting/programming languages
  • Must be fluent in Verilog, C, and/or C++
  • Knowledge of SystemVerilog/UVM or SystemC is a plus
  • Knowledge of DSP algorithms and modulation techniques such as QAM is a plus
  • Lab silicon validation experience is a plus
  • Proven track record of a high level of innovation
  • Self-motivation and the ability to execute effectively without supervision
  • Knowledge of Formal Verification methodologies and tools such as Jasper a plus.

 

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or veteran status