Principal ASIC Physical Design Timing Engineer at Acacia Communications
Maynard, MA, US

Acacia Communications is an optical networking technology company that empowers cloud and content providers to connect at the speed of light enabling them to meet the rapidly increasing consumer demands for data.

 

Reports To: Manager, ASIC Physical Design
Location: Maynard, MA

 

Responsibilities include:

  • Deliver on static timing analysis (STA) methodology and flow.  Involve major stakeholders across analog and digital teams to drive timing optimization and signoff process corner decisions. 
  • Research and drive latest timing technologies into Acacia, like latest on-chip variation modeling techniques. 
  • Own and deliver extraction methodology and flow.  
  • Run signoff timing analysis at the top level, drive closure of timing across the team. 
  • Interface with EDA vendors on issues/features/enhancements on timing tools.
  • Deliver on physical design implementation activities such as floor-planning & partitioning, synthesis, place & route, static timing analysis (STA), formal equivalence check, Clock Tree Synthesis, timing closure, signal integrity, power grid analysis, physical verification DRC/LVS across all major EDA tool suites.
  • Work closely with RTL designers to debug and root-cause Physical Implementation issues related to design and tools etc. and arrive at a feasible solution through the augmentation of input and design collateral.
  • Will be a primary member of a team responsible for executing project deliverables and processes necessary to successfully specify, develop, and release to production highly integrated ASICs.

 

 

Job requirements/skills

  • Minimum of BSEE, 8+ years of experience
  • Candidates are required to be familiar with industry standard Timing methodologies and tools from Cadence, Synopsys and/or Mentor
  • Experience in advanced technology nodes: 28nm, 16nm and below
  • Good scripting skills with Perl and TCL
  • Successful execution of ASICs from product definition to production release
  • Solid analytical, communication and presentation skills
  • Self-motivated and the ability to drive without supervision

 

Other desirable skills

  • Finfet expertise
  • Prior experience in telecom design space
  • Experience with digital signal processing algorithms is a plus
  • Exceptional written & verbal communication skills

 

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or veteran status.