Acacia Communications is an optical networking technology company that empowers cloud and content providers to connect at the speed of light enabling them to meet the rapidly increasing consumer demands for data.
- Creation of SystemVerilog models and verification of RF/Mixed-Signal blocks which can be used for functional verification at block/top-level.
- Build real numbered analog behavioral models, monitors, and checkers for RF/Mixed-Signal blocks.
- Review specifications, extract features, define and execute verification plan.
- Debug failures, fix testbench/model/checker issues, manage bug tracking, and analyze and close coverage.
- Write scripts for automation of flow
- Desired Skills and Experience:
- Expertise building Mixed-Signal testbenches, checkers and tests.
- Expertise creating and using real-numbered analog behavioral models in SystemVerilog or other language.
- Experience in HVL and HDL (SystemVerilog, Verilog)
- Understanding of common analog/RF blocks like ADC/DAC/PLLs etc.
- Experience with signal processing using Python or Matlab a plus.
- Experience with Virtuoso Composer, ADE and HED.
- Team spirit, excellent communication skills and strong problem solver
BS or MS in Electrical Engineering (or similar) with a minimum of 5 years of relevant experience
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or veteran status.